VHDL and Verilog Test Bench Synthesis - SynaptiCAD Inc.

Rev 1.1Apr 2002  SNUG 2001(San Jose)Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock DesignsRev 1.1Mar 2001Voted Best Paper3rd PlaceSNUG 2000(Boston)Coding And Scripting Techniques For FSM Designs With Synthesis-Optimized, Glitch-Free OutputsRev 1.2May 2002Voted Best Paper2nd PlaceSNUG 2000(San Jose)Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!

Yosys is a framework for Verilog RTL synthesis

Verilog is such a simple language; you could easily write code which is easy to understand and easy to map to gates. Code which uses if, case statements is simple and cause little headaches with synthesis tools. But if you like fancy coding and like to have some trouble, ok don't be scared, you could use them after you get some experience with Verilog. Its great fun to use high level constructs, saves time.

Verilog examples useful for FPGA & ASIC Synthesis

Rev 1.1Sep 2003Voted Best Paper3rd PlaceSNUG 2003(Boston)Asynchronous & Synchronous ResetDesign Techniques - Part DeuxRev 1.1Sep 2003  SNUG 2003(San Jose)Synthesizable Finite State Machine Design TechniquesUsing the New SystemVerilog 3.0 EnhancementsRev 1.1Mar 2003Voted Best Paper2nd PlaceSNUG 2002(Boston)Verilog Nonblocking Assignments With Delays, Myths & MysteriesRev 1.3Dec 2002Voted Best Paper2nd PlaceSNUG 2002(San Jose)Simulation and Synthesis Techniques for Asynchronous FIFO Designwith Asynchronous Pointer ComparisonsRev 1.1Apr 2002Voted Best Paper1st PlaceSNUG 2002(San Jose)Simulation and Synthesis Techniques for Asynchronous FIFO DesignRev 1.1Apr 2002  SNUG 2002(San Jose)Synchronous Resets?