Universal Verification Methodology | Verification Academy

N2 - This paper proposes an extended Finite State Machine with Datapath (FSMD) partitioning that performs three-dimensional (3D) high level synthesis (HLS) with objectives to minimize the number of through-silicon-via (TSV) and to equip the synthesized system with power gating capability to save power. The original FSMD partitioning was proposed for conventional low-power 2D system and was only employed before HLS. Our extended FSMD partitioning problem is formulated using integer linear programming (ILP) to minimize TSVs under constraints of footprint area, power limit, number of die stacks and HLS rules. Case study has been conducted on Discrete Cosine Transform (DCT) circuit to evaluate the effectiveness of the proposed method in terms of number of TSVs and power dissipation. Besides, power gating capability is verified and analyzed.

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This paper proposes an extended Finite State Machine with Datapath (FSMD) partitioning that performs three-dimensional (3D) high level synthesis (HLS) with objectives to minimize the number of through-silicon-via (TSV) and to equip the synthesized system with power gating capability to save power. The original FSMD partitioning was proposed for conventional low-power 2D system and was only employed before HLS. Our extended FSMD partitioning problem is formulated using integer linear programming (ILP) to minimize TSVs under constraints of footprint area, power limit, number of die stacks and HLS rules. Case study has been conducted on Discrete Cosine Transform (DCT) circuit to evaluate the effectiveness of the proposed method in terms of number of TSVs and power dissipation. Besides, power gating capability is verified and analyzed.


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Ellibs E-kirjakauppa - E-kirja: Low Power Design with High-Level Power Estimation and Power-Aware Synthesis - Tekijä: Ahuja, Sumit - Hinta: 132,70€